Method for fabricating thin film transistor array substrate and thin film transistor array substrate

ABSTRACT

After forming a gate electrode ( 4   a ) in a first step, a gate insulating film ( 5 ), a semiconductor film ( 8 ) and a conducting film ( 12 ) including a transparent conducting film ( 9 ) are stacked, and on the thus obtained multilayered body ( 18 ), a resist pattern ( 13   a ) including a first opening ( 14   a ) for exposing the conducting film ( 12 ) therein and a second opening ( 14   b ) having a bottom portion (B) above the gate electrode ( 4   a ) is formed. Portions of the conducting film ( 12 ) and the semiconductor film ( 8 ) exposed in the first opening ( 14   a ) are etched, the bottom portion (B) of the second opening ( 14   b ) is removed for exposing the conducting film ( 12 ) therein, and the exposed conducting film ( 12 ) is etched, so as to form a TFT ( 20 ) in a second step. A pixel electrode ( 5   a ), a protection masking layer ( 17   a ) and a projection ( 17   b ) are formed in a third step.

TECHNICAL FIELD

The present invention relates to a method for fabricating a thin filmtransistor array substrate and a thin film transistor array substrate,and more particularly, it relates to a thin film transistor arraysubstrate included in an MVA liquid crystal display.

BACKGROUND ART

A liquid crystal display has various merits such as compactness,thinness, low power consumption and lightness and is widely used in avariety of electronic equipment. In particular, an active matrix liquidcrystal display including a thin film transistor (TFT) as a switchingelement of each pixel has display performance equivalent to that of aCRT, and therefore, it is widely used in OA equipment such as a personalcomputer, AV equipment such as a television and a cellular phone.Particularly, the performance has been recently rapidly improved forattaining a large screen size, high refinement and a high apertureratio.

With respect to an active matrix liquid crystal display thus applied inmore fields, there is a demand for a lower price. In particular, variousexaminations have been made on methods for lowering the price byreducing the fabrication cost through improvement of productivity of aTFT array substrate included in an active matrix liquid crystal display,and among these methods, a method for reducing the number ofphotolithography processes employing photolithography, that is one offabrication processes for a TFT array substrate, has been widelystudied.

The photolithography process includes a series of steps of (1) applyinga resist on a substrate having a thin film thereon; (2) forming a latentimage of a mask pattern on the resist through optical exposure using aphotomask; (3) patterning the resist through development and etching thethin film; and (4) removing the resist. This is an indispensablefabrication process in the fabrication of a TFT array substrate.

For example, each of Patent Documents 1, 2, 3 and 4 discloses a methodfor fabricating a transmission TFT array substrate in which the numberof photolithography processes is reduced to four.

Also, each of Patent Documents 5, 6, 7 and 8 discloses a method forfabricating a transmission TFT array substrate in which the number ofphotolithography processes is reduced to three.

However, each of Patent Documents 5, 6 and 8 makes no detaileddescription on formation of a pixel electrode included in a pixel or anexternal leading electrode, and when the formation of such an element isconsidered, at least one photolithography process is necessary, whichmakes the number of photolithography processes four or more.

Moreover, Patent Document 7 discloses a method for fabricating atop-gate type TFT array, in which a channel portion of a semiconductorlayer included in a TFT is not masked from light entering through aninsulating substrate. Therefore, this technique has a problem that aphotodielectric leakage current is caused so as to disadvantageouslylower an on/off ratio (that is, a ratio between a current passing in anon state and a leakage current caused in an off state in switching adrain current in accordance with a gate voltage).

Furthermore, as known technique employed in a conventional liquidcrystal display, a masking region designated as a black matrix is formedby using chromium or a black resin on a counter substrate disposed tooppose a TFT array substrate so as to overlay TFTs, gate lines andsource lines provided on the TFT array substrate, and the TFT arraysubstrate and the counter substrate are aligned to each other so as toprevent light from entering the TFTs and suppress occurrence of aphotodielectric leakage current.

However, in consideration of an alignment margin in aligning the TFTarray substrate and the counter substrate, it is necessary to form alarge masking region, which disadvantageously lowers the aperture ratioof a pixel.

Therefore, in an attempt made to suppress the lowering of the apertureratio of a pixel, a black matrix of a counter substrate is omitted byforming a masking film like a black resist on a TFT array substrate soas to cover TFTs, gate lines and source lines, so that the TFT arraysubstrate and the counter substrate can be easily aligned.

Thus, the number of photolithography processes necessary to perform inthe fabrication of the TFT array substrate is further increased by onefor forming the masking film.

As described so far, at least four or more photolithography processesare necessary to perform in the fabrication of a TFT array substrateincluded in a transmission liquid crystal display.

In a liquid crystal display with a comparatively large screen used in amonitor of a personal computer or a liquid crystal television, verticalalignment (VA) having a multi-domain, that is, what is called MVA(multi-domain vertical alignment), has been recently widely spread (see,for example, Patent Documents 9, 10 and 11).

In an MVA liquid crystal display, at least either a pixel electrodeprovided on a TFT array substrate or a common electrode provided on acounter substrate is provided with a cut pattern (an electrode opening)or a projection for controlling orientation of liquid crystal molecules.In the MVA liquid crystal display, a wide viewing angle is realized bydispersing orientation directions of liquid crystal molecules in a pixelby using a fringe field formed by the cut pattern or inclinedorientation of the liquid crystal molecules obtained on an inclinedportion of the projection.

Also with respect to such an MVA liquid crystal display with highdisplay quality, it is desired to lower the fabrication cost forlowering the price by reducing the number of photolithography processesfor improving the productivity of a TFT array substrate as describedabove.

Patent Document 1: Japanese Laid-Open Patent Publication No. 9-152626

Patent Document 2: Japanese Laid-Open Patent Publication No. 9-236827

Patent Document 3: Japanese Laid-Open Patent Publication No. 2000-258799

Patent Document 4: Japanese Laid-Open Patent Publication No. 2001-5038

Patent Document 5: Japanese Laid-Open Patent Publication No. 3-60042

Patent Document 6: Japanese Laid-Open Patent Publication No. 8-242004

Patent Document 7: Japanese Laid-Open Patent Publication No. 2001-188252

Patent Document 8: Japanese Laid-Open Patent Publication No. 2002-343811

Patent Document 9: Japanese Laid-Open Patent Publication No. 2001-83523

Patent Document 10: Japanese Laid-Open Patent Publication No. 2001-21894

Patent Document 11: Japanese Laid-Open Patent Publication No.2001-109009

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

The present invention was devised in consideration of theabove-described situation, and an object of the invention is shorteningthe fabrication process and reducing the fabrication cost of a thin filmtransistor array substrate included in an MVA liquid crystal display byreducing the number of photolithography processes as compared with thatin a conventional fabrication method.

Means for Solving Problems

According to the present invention, the number of photolithographyprocesses performed in the fabrication process of a thin film transistorarray substrate is reduced to three.

Specifically, the method for fabricating a thin film transistor arraysubstrate of this invention is a method for fabricating a thin filmtransistor array including a plurality of pixels provided on asubstrate; a plurality of thin film transistors each of which isdisposed correspondingly to each of the plurality of pixels and includesa gate electrode, a source electrode, a drain electrode and asemiconductor layer having a channel portion formed correspondingly tothe gate electrode; a source line connected to the source electrode; apixel electrode connected to the drain electrode for applying a voltagethrough a liquid crystal layer including liquid crystal molecules; and aprojection provided in the pixel electrode for controlling orientationof the liquid crystal molecules, and the method includes a first step offorming a pattern of the gate electrode on the substrate byphotolithography; a second step of forming a pattern of the thin filmtransistors by forming a multilayered body by stacking, on the substratewhere the gate electrode has been formed, a gate insulating film, asemiconductor film to be made into the semiconductor layer and aconducting film including a transparent conducting film and covering thesemiconductor film, and by patterning the multilayered body byphotolithography; and a third step of forming a protection layercovering the thin film transistors and the projection and of forming thepixel electrode by exposing a part of the transparent conducting film byphotolithography, and the second step includes a resist pattern formingprocedure for forming a resist film covering the multilayered body, andforming, in the resist film, a first opening exposing the conductingfilm therein and disposed above a portion other than a region where thechannel portion, the source line, the source electrode and the drainelectrode are formed, and a second opening having a bottom portion witha given thickness and disposed above a portion of the multilayered bodycorresponding to the channel portion; a first etching procedure foretching the conducting film exposed in the first opening and thesemiconductor film disposed beneath the conducting film; and a secondetching procedure for removing the bottom portion of the second openingfor etching the conducting film exposed therein.

In this fabrication method, the pattern of the gate electrode is firstformed in the first step.

Next, in the second step, the multilayered body is formed by stackingthe gate insulating film, the semiconductor film and the conducting filmincluding the transparent conducting film and covering the semiconductorfilm in this order on the substrate where the gate electrode has beenformed, and after forming a resist film so as to cover the multilayeredbody, the first opening exposing the conducting film therein anddisposed above a portion other than a region where the channel portion,the source line, the source electrode and the drain electrode are formedand the second opening having a bottom portion with a given thicknessand disposed above a portion of the multilayered body corresponding tothe channel portion are formed in the resist film, so as to form aresist pattern.

Then, after etching the conducting film exposed in the first opening ofthe resist pattern and the semiconductor film disposed beneath theconducting film, the bottom portion of the second opening is removed forexposing the conducting film therein and the conducting film exposedtherein is etched, so as to form the pattern of the thin filmtransistor.

Subsequently, the protection layer covering the thin film transistor andthe projection used for controlling the orientation of the liquidcrystal molecules are formed and the pixel electrode is formed byexposing a part of the transparent conducting film in the third step.

Thus, the thin film transistor array substrate can be fabricated throughthe three photolithography processes of the first, second and thirdsteps. Therefore, the fabrication process can be shortened and thefabrication cost can be reduced for a TFT array substrate included in anMVA liquid crystal display.

The conducting film may have a masking property, and a portion of theconducting film disposed inside the periphery of the drain electrode maybe etched in the third step.

In this fabrication method, since the pixel electrode is formed byetching the portion of the conducting film disposed inside the peripheryof the drain electrode, the peripheral portion of the pixel electrodewith a transmission property is masked with the drain electrode made ofthe conducting film with the masking property. Therefore, light leakagebetween pixel electrodes can be suppressed.

The semiconductor film may include an upper first semiconductor film anda lower second semiconductor film, and the exposed conducting film andthe first semiconductor film may be etched in the second etchingprocedure.

In this fabrication method, in the case where the upper firstsemiconductor film is, for example, an n+ amorphous silicon film and thelower second semiconductor film is an intrinsic amorphous silicon film,the conducting film exposed by removing the bottom portion of the secondopening and the n+ amorphous silicon film used as the firstsemiconductor film are etched in the second etching procedure, so thatthe intrinsic amorphous silicon film used as the second semiconductorfilm is exposed, and thus the channel portion is formed.

A masking layer may be formed as an upper layer or a lower layer of theprotection layer, and the masking layer may be formed simultaneouslywith the protection layer in the third step.

In this fabrication method, since the masking layer is formed as anupper layer or a lower layer of the protection layer, the masking layeris formed simultaneously with the protection layer. Therefore, themasking layer can be formed without increasing the number ofphotolithography processes.

The protection layer may be made of a material with a masking property.

In this fabrication method, since the protection layer is made of amaterial with a masking property, there is no need to perform aprocedure for forming a masking film. Therefore, the fabrication processof the TFT array substrate can be shortened and the fabrication costthereof can be reduced.

The gate electrode may be made of a first metal laminated film includinga plurality of metal films stacked on one another, and the first metallaminated film may include a metal film made of an aluminum film or analuminum alloy film.

In this fabrication method, the first metal laminated film used forforming the gate electrode includes a metal film made of an aluminumfilm or an aluminum alloy film. In general, an aluminum film or analuminum alloy film is a low-resistance material, and hence, the wiringresistance is thus lowered.

The conducting film may include a single layer of the transparentconducting film.

In this fabrication method, since the conducting film includes a singlelayer of the transparent conducting film alone, there is no need toexpose the transparent conducting film in the third step. Therefore, thepixel electrode is formed merely by forming the protection layer in thethird step. As a result, the fabrication process of the TFT arraysubstrate can be shortened and the fabrication cost thereof can bereduced.

The conducting film may include the transparent conducting film made ofa compound of indium oxide and tin oxide, and a second metal laminatedfilm covering the transparent conducting film and including a pluralityof metal films stacked on one another, and the second metal laminatedfilm may include a lower layer of a molybdenum film or a molybdenumalloy film and an upper layer of an aluminum film or an aluminum alloyfilm.

In this fabrication method, the molybdenum film or the molybdenum alloyfilm is formed on the transparent conducting film made of the compoundof indium oxide and tin oxide (namely, an ITO film), and the aluminumfilm or the aluminum alloy film is formed on the molybdenum film or themolybdenum alloy film. Therefore, since the molybdenum film or themolybdenum alloy film is present between the aluminum film or thealuminum alloy film and the ITO film, formation of a local batterybetween the aluminum film or the aluminum alloy film and the ITO film issuppressed in etching the aluminum film or the aluminum alloy film. As aresult, electric corrosion (galvanic corrosion) between the aluminumfilm or the aluminum alloy film and the ITO film can be suppressed.

The semiconductor film may be made of a material with highertransmissivity than amorphous silicon with the same thickness.

In this fabrication method, the semiconductor film is made of a materialwith higher transmissivity than amorphous silicon with the samethickness. Furthermore, the pixel electrode is covered with thesemiconductor film. Therefore, the transmissivity of a regioncorresponding to the pixel electrode can be improved.

A plurality of gate lines each connected to the gate electrode and agate line external leading electrode corresponding to an extendedportion of each gate line may be formed simultaneously with the gateelectrode in the first step.

In this fabrication method, the plural gate lines and the gate lineexternal leading electrode corresponding to the extended portion of thegate line are simultaneously formed with the gate electrode, andtherefore, the gate lines and the gate line external leading electrodeare formed without increasing the number of fabrication processes. As aresult, the fabrication process of the TFT array substrate can beshortened and the fabrication cost thereof can be reduced.

The gate electrode, the gate line and the gate line external leadingelectrode may be made of a first metal laminated film including aplurality of metal films stacked on one another, the first metallaminated film may include a titanium film or a titanium alloy film as alowermost layer, and a portion of the titanium film or the titaniumalloy film corresponding to the gate line external leading electrode maybe exposed by etching in the third step.

In this fabrication method, the gate line external leading electrode ismade of a titanium film or a titanium alloy film. Since the titaniumfilm or the titanium alloy film is a material minimally oxidized,oxidation of the gate line external leading electrode is suppressed.

The first metal laminated film may include the titanium film or thetitanium alloy film as the lowermost layer, a metal film made of analuminum film or an aluminum alloy film, and a molybdenum film or amolybdenum alloy film covering the metal film.

In this fabrication method, since the molybdenum film or the molybdenumalloy film is easily etched with an etching used in etching the aluminumfilm or the aluminum alloy film, the gate line external leadingelectrode is definitely formed with the titanium film or the titaniumalloy film corresponding to the lowermost layer of the first metallaminated film allowed to remain.

Furthermore, since the molybdenum film or the molybdenum alloy film ispresent on the metal film made of the aluminum film or the aluminumalloy film, formation of a projection (a hillock) on the aluminum filmor the aluminum alloy film is suppressed by the molybdenum film or themolybdenum alloy film. Therefore, for example, interlayer leakageotherwise caused by a hillock penetrating an insulating film can bereduced.

Furthermore, the first metal laminated film includes the metal film madeof the aluminum film or the aluminum alloy film. Therefore, since thealuminum film or the aluminum alloy film is a low-resistance material,the wiring resistance is lowered.

The gate electrode, the gate line and the gate line external leadingelectrode may be made of a first metal laminated film including aplurality of metal films stacked on one another, and the first metallaminated film may include a titanium film or a titanium alloy film asan uppermost layer.

In this fabrication method, a titanium film or a titanium alloy film isless oxidized than, for example, the metal film made of the aluminumfilm or the aluminum alloy film, the oxidation of the gate line externalleading electrode is suppressed. Therefore, differently from the casewhere the metal film of the aluminum film or the aluminum alloy film,which is easily oxidized, is exposed, there is no need to etch the metalfilm easily oxidized in a portion corresponding to the gate lineexternal leading electrode, and hence, the fabrication process isshortened and the fabrication cost is reduced.

The first metal laminated film may include an aluminum film or analuminum alloy film, and portions of the protection layer and the gateinsulating film disposed inside the periphery of the gate line externalleading electrode may be etched in the third step.

In this fabrication method, the portions of the protection layer and thegate insulating film disposed inside the periphery of the gate lineexternal leading electrode are etched, and hence, the aluminum film orthe aluminum alloy film included in the first metal laminated film isnot exposed. Also, since the uppermost layer of the first metallaminated film exposed through the etching is the titanium film or thetitanium nitride film minimally oxidized, the gate line external leadingelectrode has a structure minimally oxidized.

The source line and a source line external leading electrodecorresponding to an extended portion of the source line may be formedalong a direction crossing the plurality of gate lines simultaneouslywith the source electrode in the second step.

In this fabrication method, since the source line and the source lineexternal leading electrode corresponding to the extended portion of thesource line are formed simultaneously with the source electrode, thesource line and the source line external leading electrode are formedwithout increasing the number of fabrication processes. As a result, thefabrication process of the TFT array substrate can be shortened and thefabrication cost thereof can be reduced.

The gate electrode, the gate line and the gate line external leadingelectrode may be made of a first metal laminated film including aplurality of metal films stacked on one another, the source electrode,the source line and the source line external leading electrode may bemade of a second metal laminated film including a plurality of metalfilms stacked on one another, and at least uppermost layers of the firstmetal laminated film and the second metal laminated film may be removedby etching in portions corresponding to the gate line external leadingelectrode and the source line external leading electrode in the thirdstep.

In this fabrication method, at least the uppermost layers of portions ofthe multilayered films corresponding to the gate line external leadingelectrode and the source line external leading electrode are removedsimultaneously with the formation of the pixel electrode, themultilayered structures of the portion corresponding to the gate lineexternal leading electrode and the source line external leadingelectrode are changed without increasing the number of fabricationprocesses. As a result, the fabrication process of the TFT arraysubstrate can be shortened and the fabrication cost thereof can bereduced.

The uppermost layer of each of the first metal laminated film and thesecond metal laminated film may be made of an aluminum film or analuminum alloy film, or a multilayered film of a molybdenum film or amolybdenum alloy film stacked on an aluminum film or an aluminum alloyfilm.

In this fabrication method, the uppermost layers of portions of themultilayered films corresponding to the gate line external leadingelectrode and the source line external leading electrode are made of thealuminum film or the aluminum alloy film, or the multilayered film ofthe molybdenum film or the molybdenum alloy film stacked on the aluminumfilm or the aluminum alloy film. Therefore, the gate line externalleading electrode and the source line external leading electrode areformed simultaneously with the formation of the pixel electrode, andhence, the fabrication process of the TFT array substrate can beshortened and the fabrication cost thereof can be reduced.

At this point, in the case where the uppermost layers of themultilayered films are made of the aluminum film or the aluminum alloyfilm, the aluminum film or the aluminum alloy film easily oxidized isremoved, so as to suppress the oxidation of the gate line externalleading electrode and the source line external leading electrode.

Alternatively, in the case where the uppermost layers of themultilayered films are made of the multilayered film of the molybdenumfilm or the molybdenum alloy film stacked on the aluminum film or thealuminum alloy film, the molybdenum film or the molybdenum alloy filmstacked on the aluminum film or the aluminum alloy film suppresses theformation of a projection (a hillock) on the aluminum film or thealuminum alloy film.

Furthermore, in the case where an ITO film is formed beneath themolybdenum film or the molybdenum alloy film, since the molybdenum filmor the molybdenum alloy film is present between the aluminum film or thealuminum alloy film and the ITO film, formation of a local batterybetween the aluminum film or the aluminum alloy film and the ITO film issuppressed in etching the aluminum film or the aluminum alloy film. As aresult, electric corrosion (galvanic corrosion) between the aluminumfilm or the aluminum alloy film and the ITO film can be suppressed.

The protection layer may have a masking property and cover the thin filmtransistors, the gate line and the source line.

In this fabrication method, since the protection layer having a maskingproperty is formed so as to cover the thin film transistor, the gateline and the source line, the protection layer prevents light fromentering the thin film transistor (TFT) as well as functions as amasking pattern between pixels (namely, a black matrix). Therefore,there is no need to provide a black matrix on a counter substrategenerally disposed to oppose the TFT array substrate, and hence, thefabrication process of the counter substrate is shortened. Also,occurrence of light leakage between pixels derived from an alignmentshift between the TFT array substrate and the counter substrate and aphotoleakage current in a TFT can be suppressed.

The gate line external leading electrode and the source line externalleading electrode may be exposed by forming one opening correspondinglyto at least one of the gate line external leading electrode and thesource line external leading electrode by etching.

In this fabrication method, since each of the external leading terminalsis exposed by forming one opening correspondingly to at least one of thegate line external leading electrode and the source line externalleading electrode, no layer is present on and between the externalleading terminals. Therefore, an external driver circuit can be easilyand stably connected to each of the external leading terminals by, forexample, a TAB (tape automated bonding) method. Furthermore, in the casewhere an external driver circuit is connected by forming an opening ineach of the external leading electrodes, it is apprehended that aportion of a thin film disposed in the vicinity of the bottom of theopening may be peeled off so as to form an unstable cross-sectionalstructure designated as an overhang. Since each external leadingelectrode is exposed in one opening in this embodiment, an overhang canbe avoided so as to attain stable connection with an external drivercircuit.

A protection film included in the protection layer and the gateinsulating film may be etched in portions outside the periphery of thedrain electrode in the third step.

For example, in the case where the semiconductor film to be etched inthe first etching procedure is not completely etched, it is apprehendedthat a part of the semiconductor film may remain between the pixelelectrode and the source line. However, in the aforementioned method,when the semiconductor film and the gate insulating film are made ofmaterials simultaneously etched, the remaining part of the semiconductorfilm is etched simultaneously with the gate insulating film in etchingthe protection film included in the protection layer and the gateinsulating film in the portions disposed outside the periphery of thedrain electrode in the third step. Therefore, a short-circuit betweenthe pixel electrode and the source line is suppressed.

Also, the thin film transistor array substrate of this inventionincludes a plurality of pixels provided on a substrate; a plurality ofthin film transistors each of which is disposed correspondingly to eachof the plurality of pixels and includes a gate electrode, a sourceelectrode, a drain electrode and a semiconductor layer having a channelportion formed correspondingly to the gate electrode; a source lineconnected to the source electrode; a pixel electrode connected to thedrain electrode for applying a voltage through a liquid crystal layerincluding liquid crystal molecules; and a projection provided in thepixel electrode for controlling orientation of the liquid crystalmolecules, and the thin film transistor array substrate is fabricatedthrough a first step of forming a pattern of the gate electrode on thesubstrate by photolithography; a second step of forming a pattern of thethin film transistors by forming a multilayered body by stacking, on thesubstrate where the gate electrode has been formed, a gate insulatingfilm, a semiconductor film to be made into the semiconductor layer and aconducting film including a transparent conducting film and covering thesemiconductor film, and patterning the multilayered body byphotolithography; and a third step of forming a protection layercovering the thin film transistors and the projection and of forming thepixel electrode by exposing a part of the transparent conducting film byphotolithography, the second step includes a resist pattern formingprocedure for forming a resist film covering the multilayered body, andforming, in the resist film, a first opening exposing the conductingfilm therein and disposed above a portion other than a region where thechannel portion, the source line, the source electrode and the drainelectrode are formed, and a second opening having a bottom portion witha given thickness and disposed above a portion of the multilayered bodycorresponding to the channel portion; a first etching procedure foretching the conducting film exposed in the first opening and thesemiconductor film disposed beneath the conducting film; and a secondetching procedure for removing the bottom portion of the second openingfor etching the conducting film exposed therein, and the semiconductorfilm and the conducting film covering the semiconductor film areprovided beneath the projection.

Effects of Invention

According to the present invention, a thin film transistor arraysubstrate can be fabricated through the first step, the second step andthe third step, namely, three photolithography processes, and therefore,the fabrication process is shortened and the fabrication cost is reducedfor a thin film transistor array substrate included in an MVA liquidcrystal display.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic plan view of a TFT array substrate 30 a ofEmbodiment 1.

FIG. 2 is a schematic cross-sectional view, taken on line II-II of FIG.1, of a substrate on which a first metal laminated film 19 a is formedin a gate electrode forming procedure of Embodiment 1.

FIG. 3 is a schematic cross-sectional view of the substrate on which agate electrode 4 a is formed in the gate electrode forming procedure ofEmbodiment 1.

FIG. 4 is a schematic cross-sectional view of the substrate on which amultilayered body 18 is formed in a multilayered body forming procedureof Embodiment 1.

FIG. 5 is a schematic cross-sectional view of the substrate on which aresist pattern 13 a is formed in a first resist pattern formingprocedure of Embodiment 1.

FIG. 6 is a schematic cross-sectional view of the substrate etched byusing the first resist pattern 13 a in a first etching procedure ofEmbodiment 1.

FIG. 7 is a schematic cross-sectional view of the substrate on which asecond resist pattern 13 b is formed in a second resist pattern formingprocedure of Embodiment 1.

FIG. 8 is a schematic cross-sectional view of the substrate etched byusing the second resist pattern 13 b in a second etching procedure ofEmbodiment 1.

FIG. 9 is a schematic cross-sectional view of the substrate on which aprotection film 15 and an orientation controlling film 16 aresuccessively formed in a pixel electrode forming procedure of Embodiment1.

FIG. 10 is a schematic cross-sectional view of the substrate on which apixel electrode 9 d, a protection masking layer 17 a and a projection 17b are formed in the pixel electrode forming procedure of Embodiment 1,corresponding to a schematic cross-sectional view of the active matrixsubstrate 30 a.

FIG. 11 is a schematic plan view of an end portion of the TFT arraysubstrate 30 a of Embodiment 1 showing a gate line external leadingterminal 4 c.

FIG. 12 is a schematic cross-sectional view of the TFT array substrate30 a taken on line XII-XII of FIG. 11.

FIG. 13 is a schematic cross-sectional view, corresponding to FIG. 12,of the substrate on which the protection film 15 and the orientationcontrolling film 16 are successively formed in the pixel electrodeforming procedure of Embodiment 1.

FIG. 14 is a schematic cross-sectional view, corresponding to FIG. 12,of the substrate on which the pixel electrode 9 d, the protectionmasking layer 17 a and the projection 17 b are formed in the pixelelectrode forming procedure of Embodiment 1.

FIG. 15 is a schematic plan view of an end portion of the TFT arraysubstrate 30 a of Embodiment 1 showing a source line external leadingterminal 12 g.

FIG. 16 is a schematic cross-sectional view of the TFT array substrate30 a taken on line XVI-XVI of FIG. 15.

FIG. 17 is a schematic cross-sectional view, corresponding to FIG. 16,of the substrate on which the protection film 15 and the orientationcontrolling film 16 are successively formed in the pixel electrodeforming procedure of Embodiment 1.

FIG. 18 is a schematic cross-sectional view, corresponding to FIG. 16,of the substrate on which the pixel electrode 9 d, the protectionmasking layer 17 a and the projection 17 b are formed in the pixelelectrode forming procedure of Embodiment 1.

FIG. 19 is a schematic cross-sectional view of a substrate on which afirst metal laminated film 19 a is formed in a gate electrode formingprocedure of Embodiment 2.

FIG. 20 is a schematic cross-sectional view of the substrate on which agate electrode 4 a is formed in the gate electrode forming procedure ofEmbodiment 2.

FIG. 21 is a schematic cross-sectional view of the substrate on which amultilayered body 18 is formed in a multilayered body forming procedureof Embodiment 2.

FIG. 22 is a schematic cross-sectional view of the substrate on which aresist pattern 13 a is formed in a first resist pattern formingprocedure of Embodiment 2.

FIG. 23 is a schematic cross-sectional view of the substrate etched byusing the first resist pattern 13 a in a first etching procedure ofEmbodiment 2.

FIG. 24 is a schematic cross-sectional view of the substrate on which asecond resist pattern 13 b is formed in a second resist pattern formingprocedure of Embodiment 2.

FIG. 25 is a schematic cross-sectional view of the substrate etched byusing the second resist pattern 13 b in a second etching procedure ofEmbodiment 2.

FIG. 26 is a schematic cross-sectional view of the substrate on which aprotection film 15 and an orientation controlling film 16 aresuccessively formed in a pixel electrode forming procedure of Embodiment2.

FIG. 27 is a schematic cross-sectional view of the substrate on which apixel electrode 25 d, a protection masking layer 17 a and a projection17 b are formed in the pixel electrode forming procedure of Embodiment2, corresponding to a schematic cross-sectional view of an active matrixsubstrate 30 b.

FIG. 28 is a schematic plan view of an end portion of the TFT arraysubstrate 30 b of Embodiment 2 showing a gate line external leadingelectrode 4 b.

FIG. 29 is a schematic cross-sectional view of the TFT array substrate30 b taken on line XXIX-XXIX of FIG. 28.

FIG. 30 is a schematic cross-sectional view corresponding to FIG. 13obtained in a pixel electrode forming procedure described as acomparative example of Embodiment 1.

FIG. 31 is a schematic cross-sectional view corresponding to FIG. 14obtained in a pixel electrode forming procedure described as acomparative example of Embodiment 1.

FIG. 32 is a schematic cross-sectional view corresponding to FIG. 12obtained in a pixel electrode forming procedure described as acomparative example of Embodiment 1.

FIG. 33 is a schematic cross-sectional view corresponding to FIG. 17obtained in a pixel electrode forming procedure described as acomparative example of Embodiment 1.

FIG. 34 is a schematic cross-sectional view corresponding to FIG. 18obtained in a pixel electrode forming procedure described as acomparative example of Embodiment 1.

FIG. 35 is a schematic cross-sectional view corresponding to FIG. 16obtained in a pixel electrode forming procedure described as acomparative example of Embodiment 1.

DESCRIPTION OF REFERENCE NUMERALS

-   -   B bottom portion    -   C channel portion    -   1 insulating substrate    -   2, 21 gate first metal film    -   3, 22 gate second metal film    -   4 gate line    -   4 a gate electrode    -   4 b gate line external leading electrode    -   5 gate insulating film    -   6 intrinsic amorphous silicon film (second semiconductor film)    -   7 n⁺ amorphous silicon film (first semiconductor film)    -   8, 24 semiconductor film    -   8 a, 24 a semiconductor layer    -   9, 25 transparent conducting film    -   9 d, 25 d pixel electrode    -   12 conducting film    -   12 b source line    -   12 c, 25 b source electrode    -   12 e, 25 c drain electrode    -   12 f source line external leading electrode    -   13 a first resist pattern    -   13 b second resist pattern    -   14 a first opening    -   14 b second opening    -   15 a protection layer    -   16 a masking layer    -   17 b projection    -   17 c opening    -   18 multilayered body    -   19 a fist metal laminated film    -   19 b second metal laminated film    -   20 thin film transistor (TFT)    -   23 gate third metal film    -   30 a, 30 b thin film transistor array substrate

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the invention will now be described with reference to theaccompanying drawings. It is noted that the present invention is notlimited to the embodiments described below.

Embodiment 1

A thin film transistor (TFT) array substrate 30 a according toEmbodiment 1 of the invention will now be described.

FIG. 1 is a schematic plan view of one pixel of the TFT array substrate30 a. The TFT array substrate 30 a is included in a liquid crystaldisplay together with an opposing counter substrate and a liquid crystallayer sandwiched between these substrates. It is noted that the liquidcrystal layer has negative dielectric constant anisotropy (Δ_(∈)<0) andis made of nematic liquid crystal (liquid crystal molecules) of avertical alignment type.

The TFT array substrate 30 a includes, on an insulating substrate 1, aplurality of gate lines 4 extending in parallel and a plurality ofsource lines 12 b extending in parallel and perpendicular to the gatelines 4 as shown in FIG. 1. A TFT 20 is provided on each crossingportion between the gate lines 4 and the source lines 12 b. Furthermore,a pixel electrode 9 d included in each pixel is provided correspondinglyto each TFT 20 in a display region surrounded with a pair of gate lines4 and a pair of source lines 12 b. The pixel electrode 9 d ispartitioned by a projection 17 b provided for controlling theorientation of the liquid crystal molecules. Moreover, an alignment film(not shown) is provided on the pixel electrode 9 d. In addition, ends ofeach gate line 4 and each source line 12 b are respectively providedwith a gate line external leading terminal 4 c and a source lineexternal leading terminal 12 g described below.

The TFT 20 includes, as shown in FIG. 10, a gate electrode 4 a made of aconvex protruded sideways from the gate line 4; a semiconductor layer 8a provided above the gate electrode 4 a with a gate insulating film 5sandwiched therebetween; a source electrode 12 c made of a convexprotruded sideways from the source line 12 b on the semiconductor layer8 a; and a drain electrode 12 e opposing the source electrode 12 c onthe semiconductor layer 8 a and connected to the pixel electrode 9 d. Inthe semiconductor layer 8 a, a channel portion C is providedcorrespondingly to the gate electrode 4 a in a region between the sourceelectrode 12 c and the drain electrode 12 e. Furthermore, a protectionmasking layer 17 a composed of a protection layer 15 a and a maskinglayer 16 a is provided so as to cover the TFT 20. The protection maskinglayer 17 a is provided so as to cover also the gate lines 4 and thesource lines 12 b.

The projection 17 b extends from the protection masking layer 17 adisposed on the gate lines 4 and the source lines 12 b and is providedso as to extend in an oblique direction against the extending directionsof the gate lines 4 and the source lines 12 b. The orientation of theliquid crystal molecules is divided by this projection 17 b in onepixel, so as to increase the viewing angle of the liquid crystaldisplay, namely, so as to realize an MVA (multi-domain verticalalignment) liquid crystal display.

Furthermore, although pixels are arranged in the form of a matrix andthe gate lines 4 and the source lines 12 b are perpendicular to eachother in the TFT array substrate 30 a of this embodiment, the presentinvention is applicable to a TFT array substrate including pixelsprovided, for example, in delta arrangement. It is noted that Embodiment2 described below is also similarly applicable to this.

Moreover, although the gate electrode 4 a of the TFT 20 is protrudedsideways from the gate line 4 in this embodiment, the present inventionis applicable to, for example, what is called a TFT on-gate structure inwhich a channel portion of a TFT is provided on a gate line 4. It isnoted that Embodiment 2 described below is also similarly applicable tothis.

Next, a method for fabricating the TFT array substrate 30 a having theaforementioned structure will be described with reference to FIGS. 2through 10. FIGS. 2 through 10 are schematic cross-sectional views takenon line II-II of FIG. 1. The TFT array substrate 30 a is fabricatedthrough a first step of a gate electrode forming procedure; a secondstep including a multilayered body forming procedure, a first resistpattern forming procedure, a first etching procedure, a second resistpattern forming procedure and a second etching procedure; and a thirdstep of a pixel electrode forming procedure described below.

First, in the gate electrode forming procedure, a gate first metal film2 (with a thickness of approximately 500 Å) of a titanium film and agate second metal film 3 (with a thickness of approximately 3000 Å) ofan aluminum film are successively formed over an insulating substrate 1of a glass substrate or the like by sputtering, so as to form a firstmetal laminated film 19 a as shown in FIG. 2.

Next, the first metal laminated film 19 a is patterned byphotolithography, so as to form a gate electrode 4 a, a gate line 4 anda gate line external leading electrode 4 c composed of a gate firstmetal layer 2 a and a gate second layer 3 a.

At this point, since the metal laminated film 19 a used for forming thegate electrode 4 a includes an aluminum film or an aluminum alloy film,that is, a low-resistance material, the wiring resistance of the gateline 4 can be lowered.

Alternatively, a molybdenum film or a molybdenum alloy film may befurther patterned on the gate second metal layer 3 a of the aluminumfilm. In this manner, the molybdenum film or the molybdenum alloy filmformed on the aluminum film can suppress formation of a projection (ahillock) on the aluminum film. Therefore, occurrence of, for example,interlayer leakage otherwise caused by a hillock penetrating aninsulating film can be reduced. At this point, a hillock means aprojection formed on an aluminum film due to thermal history such asthermal process or plasma process. Moreover, the molybdenum film or themolybdenum alloy film can be easily etched with an etchant used inetching the aluminum film or the aluminum alloy film, such as a mixtureof nitric acid, phosphoric acid and acetic acid, and hence, it issimultaneously removed through etching of the aluminum film describedbelow and there is no need to perform separate etching.

In the multilayered body forming procedure subsequently performed, agate insulating film 5 (with a thickness of approximately 4000 Å) of asilicon nitride film, an intrinsic amorphous silicon film 6 (with athickness of approximately 1500 Å) and an n⁺ amorphous silicon film 7(with a thickness of approximately 500 Å) doped with an impurity such asphosphorus are successively formed by plasma CVD over the substratewhere the gate electrode 4 a and the like have been formed as shown inFIG. 4. Subsequently, a transparent conducting film 9 (with a thicknessof approximately 1000 Å) of an ITO (indium tin oxide) film, that is, acompound of indium oxide and tin oxide, a source first metal film 10(with a thickness of approximately 1000 Å) of a molybdenum film and asource second metal film 11 (with a thickness of approximately 1000 Å)of an aluminum film are successively formed over the substrate by thesputtering.

Thus, a multilayered body 18 including the gate insulating film 5, theintrinsic amorphous silicon film 6, the n⁺ amorphous silicon film 7, thetransparent conducting film 9, the source first metal film 10 and thesource second metal film 11 stacked successively in this order in theupward direction is formed. At this point, a semiconductor film 8 is amultilayered film of the intrinsic amorphous silicon film 6 and the n⁺amorphous silicon film 7, and a conducting film 12 is a multilayeredfilm of the transparent conducting film 9 and a second metal laminatedfilm 19 b composed of the source first metal film 10 and the sourcesecond metal film 11.

Also, since the molybdenum film is present between the aluminum film andthe ITO film, formation of a local battery between the aluminum film andthe ITO film can be suppressed in subsequently etching the aluminumfilm. Therefore, electric corrosion (galvanic corrosion) between thealuminum film and the ITO film can be prevented. Furthermore, thetransparent conducting film 9 is not limited to the ITO film but may beany film having a desired resistance value, such as an IZO (indium zinoxide) film, a zinc oxide film or a tin oxide film.

Moreover, although the molybdenum film is exemplarily used as the sourcefirst metal film 10 included in the second metal laminated film 19 b inthis embodiment, the source first metal film is not limited to this butmay be a titanium film, a chromium film or an alloy film such as amolybdenum alloy film. Also, although the aluminum film is exemplarilyused as the source second metal film 11 included in the second metallaminated film 19 b, the source second metal film is not limited to thisbut may be an aluminum alloy film or the like.

In the first resist pattern forming procedure subsequently performed, aresist film is formed by applying a resist made of a photosensitiveresin over the substrate so as to cover the multilayered body 18.

Then, the resist film formed over the substrate is made into a firstresist pattern 13 a having a plurality of thicknesses as shown in FIG. 5with exposure adjusted by using a slit mask or the like.

At this point, the first resist pattern 13 a includes a first opening 14a exposing therein the conducting film 12, and more specifically thesource second metal film 11, and disposed above a portion other than aregion where a channel portion C, a source line 12 b, a source electrode12 c and a drain electrode 12 d are formed; and a second opening 14 bhaving a bottom portion B with a given thickness and disposed above thegate electrode 4 a, and more specifically above a portion correspondingto the channel portion C. An appropriate ratio in the thickness betweenthe resist film in the second opening 14 b and the resist film inanother portion is varied in accordance with the conditions for etchingand ashing subsequently performed, and the resist film has a thicknessof, for example, approximately 15000 through 20000 Å in the secondopening 14 b and approximately 40000 Å in another portion.

In the first etching procedure subsequently performed, the source secondmetal film 11, the source first metal film 10 and the transparentconducting film 9 are successively wet etched and then the n⁺ amorphoussilicon film 7 and the intrinsic amorphous silicon film 6 aresuccessively dry etched by using the first resist pattern 13 a as a maskas shown in FIG. 6, so as to form a source/drain forming layer 12 acomposed of a transparent conducting layer 9 a, a source first metallayer 10 a and a source second metal layer 11 a; and a semiconductorforming layer 8 a composed of an intrinsic amorphous silicon layer 6 aand an n⁺ amorphous silicon layer 7 a.

In the second resist pattern forming procedure subsequently performed,the whole first resist pattern 13 a is ashed as shown in FIG. 7. Thus,the thickness of the first resist pattern 13 a is reduced as a whole andthe bottom portion B of the second opening 14 b is removed, resulting informing a second resist pattern 13 b in which the conducting film 12,and specifically the source second metal layer 11 a, is exposed.

In the second etching procedure subsequently performed, as shown in FIG.8, the source second metal layer 11 a, the source first metal layer 10 aand the transparent conducting layer 9 a are first wet etched by usingthe second resist pattern 13 b as a mask, so as to form a sourceelectrode 12 c composed of a transparent conducting layer 9 c, a sourcefirst metal layer 10 c and a source second metal layer 11 c; a drainelectrode forming portion 12 d composed of a transparent conductinglayer 9 b, a source first metal layer 10 b and a source second metallayer 11 b; a source line 12 b; and a source line external leadingelectrode 12 f.

Then, also by using the second resist pattern 13 b as a mask, a channelportion C is formed by dry etching an n⁺ amorphous silicon layer 6 b, soas to form a TFT 20, and thereafter, the second resist pattern 13 b isremoved.

In the pixel electrode forming procedure subsequently performed, asilicon nitride film (with a thickness of approximately 2000 Å) isdeposited over the substrate by the plasma CVD so as to form aprotection film 15.

Then, an orientation controlling film 16 (with a thickness ofapproximately 1.0 μm through 3.0 μm) is formed on the protection film 15by the spin coating or the like. At this point, examples of the materialfor the orientation controlling film are a phenol novolak positiveresist, a photosensitive acrylic resin solution and a photosensitiveepoxy resin solution. Also, the protection film 15 or the orientationcontrolling film 16 preferably has a masking property. Examples of thematerial for such an orientation controlling film are a phenol novolakpositive resist in which carbon is dispersed; and a photosensitive epoxyresin solution in which red, green and blue pigments are dispersed. Whensuch a material is used, since the protection film 15 or the orientationcontrolling film 16 is made of a material with a masking property, thereis no need to perform a procedure for forming a masking film. This canshorten the fabrication process and reduce the fabrication cost of theTFT array substrate. Furthermore, since the orientation controlling film16 is formed on the protection film 15, the protection film 15 can bepatterned by using a pattern of the orientation controlling film 16 as amask in subsequent photolithography. Thus, the protection film 15 can bepatterned without increasing the number of photolithography processes.

Thereafter, the orientation controlling film 16 formed over thesubstrate is subjected to exposure with a photomask used, developmentand post-bake, so as to form a masking layer 16 a and a projection upperportion 16 b.

Furthermore, by using the masking layer 16 a and the projection upperportion 16 b as a mask, the protection film 15 and the source secondmetal layer 11 b and the source first metal layer 10 b of the drainelectrode forming portion 12 d are etched for exposing a part of thetransparent conducting layer 9 b, so as to form a protection maskinglayer 17 a composed of the masking layer 16 a and a protection layer 15a; a drain electrode 12 e composed of a source second metal layer 11 eand a source first metal layer 10 e; a projection 17 b composed of theprojection upper portion 16 b and a projection lower portion 15 b (and asource second metal layer 11 d and a source first metal layer 10 d); anda pixel electrode 9 d. At this point, since the conducting film isetched in a portion disposed inside the periphery of the drain electrode12 e (corresponding to the drain electrode forming portion 12 d), theperiphery of the pixel electrode 9 d with a transmission property ismasked by the drain electrode 12 e made of the drain electrode formingportion 12 d with a masking property. Thus, light leakage between pixelelectrodes 9 d can be suppressed.

Furthermore, the protection masking layer 17 a is formed so as to covernot only the TFT 20 but also the gate lines 4 and the source lines 12 b.Thus, the protection masking layer 17 a having a masking propertyprevents light from entering the TFT 20 as well as functions as amasking pattern between pixels (namely, a black matrix). Therefore,there is no need to provide a black matrix on a counter substrategenerally provided to oppose the TFT array substrate, and thefabrication process of the counter substrate can be shortened. Moreover,light leakage between pixels and a photoleakage current occurring in aTFT derived from an alignment shift between the TFT array substrate andthe counter substrate can be suppressed.

The active matrix substrate 30 a is fabricated in the aforementionedmanner.

Although the protection masking layer 17 a exemplarily has a two-layeredstructure of the protection film 15 and the orientation controlling film16 in this embodiment, it may have a one-layered structure of aphotoresist with a masking property in which, for example, red, greenand blue pigments are dispersed. In this case, the masking film can beomitted and hence there is no need to perform the procedure for formingthe masking film. As a result, the fabrication process of the TFT arraysubstrate can be shortened and the fabrication cost thereof can bereduced.

Moreover, although the conducting film is exemplarily etched in theportion disposed inside the periphery of the drain electrode 12 e (thedrain electrode forming portion 12 d) in the pixel electrode formingprocedure of this embodiment, the protection film 15 (the orientationcontrolling film 16) and the gate insulating film 5 may be etched inportions disposed outside the periphery of the drain electrode 12 einstead.

Specifically, for example, in the case where the semiconductor film 8 tobe etched in the first etching procedure is not completely etched, it isapprehended that a part of the semiconductor film 8 may remain betweenthe pixel electrode 9 d and the source line 12 b. However, in etchingthe protection film 15 (the orientation controlling film 16) and thegate insulating film 5 in the portions disposed outside the periphery ofthe drain electrode 12 e in the pixel electrode forming procedure, theremaining part of the semiconductor film 8 is etched simultaneously withthe gate insulating film 5. Therefore, a short-circuit between the pixelelectrode 9 d and the source line 12 b can be prevented. It is notedthat this is also applicable to Embodiment 2 described below.

Next, the gate line external leading electrode 4 b and the source lineexternal leading electrode 12 f will be described in more detail.

FIG. 11 is a schematic plan view of an end portion of the TFT arraysubstrate 30 a in which a plurality of gate line external leadingterminals 4 c are provided, and FIG. 12 is a schematic cross-sectionalview thereof taken on line XII-XII of FIG. 11. Also, FIG. 15 is aschematic plan view of an end portion of the TFT array substrate 30 a inwhich a plurality of source line external leading terminals 12 g areprovided, and FIG. 16 is a schematic cross-sectional view thereof takenon line XVI-XVI of FIG. 15.

First, at a stage previous to the formation of the protection layer 15 aand the masking layer 16 a, the protection film 15 and the orientationcontrolling film 16 are formed on each gate line external leadingelectrode 4 b and each source line external leading electrode 12 f asshown in FIGS. 13 and 17.

Then, at the same time as the formation of the protection layer 15 a andthe masking layer 16 a, the gate insulating film 5, the protection film15 and the orientation controlling film 16 stacked on the gate lineexternal leading electrode 4 b and the protection film 15 and theorientation controlling film 16 stacked on the source line externalleading electrode 12 f are removed so as to respectively form openings17 c and 17 d. Thus, the gate line external leading electrode 4 b andthe source line external leading electrode 12 f are exposed as shown inFIGS. 14 and 18.

Furthermore, since the gate second metal layer 3 a corresponding to theuppermost layer of the gate line external leading electrode 4 b and thesource second metal layer 11 a corresponding to the uppermost layer ofthe source line external leading electrode 12 f are made of the aluminumfilms in this embodiment, at the same time as the gate line externalleading electrode 4 b and the source line external leading electrode 12f are exposed, the gate second metal layer 3 a and the source secondmetal layer 11 a (and the source first metal layer 10 b) arerespectively etched as shown in FIGS. 12 and 16, resulting in formingthe gate line external leading terminal 4 c in which the gate firstmetal layer 2 a is exposed and the source line external leading terminal12 g in which the transparent conducting layer 9 a is exposed. In thismanner, the aluminum film easily oxidized can be removed in eachexternal leading electrode, and hence, oxidation of the gate lineexternal leading electrode 4 b and the source line external leadingelectrode 12 f can be prevented.

The aluminum film (the aluminum alloy film) used for forming the gatesecond metal layer 3 a or the source second metal layer 11 a may be madeof a multilayered film of an aluminum film (an aluminum alloy film) anda molybdenum film (a molybdenum alloy film) stacked thereon.

In this case, the molybdenum film (the molybdenum ally film) stacked onthe aluminum film (the aluminum alloy film) can suppress formation of aprojection (a hillock) on the aluminum film (the aluminum alloy film).

Moreover, in the case where an ITO film is formed beneath the molybdenumfilm (the molybdenum alloy film), since the molybdenum film (themolybdenum alloy film) is present between the aluminum film (thealuminum alloy film) and the ITO film, a local battery can be preventedfrom being formed between the aluminum film (the aluminum alloy film)and the ITO film in etching the aluminum film (the aluminum alloy film),so as to prevent electric corrosion (galvanic corrosion) between thealuminum film (the aluminum alloy film) and the ITO film.

At this point, since the molybdenum film is formed as a lower layer inthe source line external leading electrode 12 f, it can be etchedsimultaneously with the aluminum film provided as an upper layer by thewet etching using, as an etchant, a mixed solution of nitric acid,phosphoric acid and acetic acid.

Furthermore, since each of the gate line external leading terminals 4 c(the gate line external leading electrodes 4 b) and the source lineexternal leading terminals 12 g (the source line external leadingelectrodes 12 f) is exposed in one opening, no thin film material ispresent on and between the gate line external leading terminals 4 c andthe source line external leading terminals 12 g as shown in FIGS. 12 and16, and hence, an overhang described below is not caused. Therefore, anexternal driver circuit can be easily and stably connected to each ofthe gate line external leading terminals 4 c and the source lineexternal leading terminals 12 g by, for example, a TAB (tape automatedbonding) method.

On the contrary, in the case where a contact hole is formed for eachexternal leading electrode for connection with an external drivercircuit, a gate second metal layer 103 a or a source first metal layer110 a and a source second metal layer 11 a are isotropically wet etchedon the bottom of the contact hole as shown in FIGS. 32 and 35, andhence, an unstable cross-sectional structure designated as an overhangin which the film can be easily peeled off because no thin film ispresent in a lower portion is caused as shown in a region X in thedrawing. Therefore, the connection between the external leadingelectrode (terminal) and the external driver circuit is unstable. It isnoted that schematic cross-sectional views of FIGS. 30 through 32 and 33through 35 respectively correspond to the schematic cross-sectionalviews of FIGS. 12 through 14 and 16 through 18.

Although the metal film corresponding to the lower layer of the firstmetal laminated film 19 a included in the gate line 4, the gateelectrode 4 a and the gate line external leading electrode 4 b isexemplarily made of a titanium film in this embodiment, the metal filmis not limited to the titanium film but may be a chromium film, amolybdenum film or the like.

However, in the case where a titanium film is used as the gate firstmetal film 2 corresponding to the lower layer of the first metallaminated film 19 a and an aluminum film or an aluminum alloy film isused as the gate second metal layer 3 stacked thereon, the gate line 4,the gate electrode 4 a and the gate line external leading electrode 4 bcan be easily patterned by the dry etching. In addition, in forming thegate line external leading terminal 4 c, the first metal laminated film19 a can be selectively etched so as to allow the lower titanium filmalone to remain through the wet etching and a portion corresponding tothe aluminum film or the aluminum alloy film stacked thereon in thefirst metal laminated film 19 a can be removed.

As described above, when the lower layer of the first metal laminatedfilm 19 a is made of a titanium film, since a titanium film is lessoxidized than an aluminum film or an aluminum alloy film, the gate lineexternal leading terminal 4 c made of the titanium film can bedefinitely electrically connected to an external driver circuit by theTAB method, and the reliability can be improved.

At this point, in the TAB method, a lead interconnect pattern of acopper foil formed in a tape-shaped film including a polyimide resin asa base is used for electrically connecting, for example, conductivematerials to each other.

Furthermore, when the gate first metal film 2 corresponding to the upperlayer of the first metal laminated film 19 a is made of an aluminum filmor an aluminum alloy film, an effect to lower the wiring resistance canbe attained, and in addition, the selective etching for allowing thetitanium film alone to remain can be definitely carried out by the wetetching.

As described so far, in the fabrication method of this embodiment, theTFT array substrate 30 a can be fabricated through the threephotolithography processes of the first, second and third stepsincluding the formation of the protection masking layer 17 a coveringthe TFT 20 and working as a black matrix between pixels, the formationof the protection 17 b for realizing the MVA and the formation of thegate line external leading terminal 4 c and the source line externalterminal 12 g. Therefore, the fabrication process can be shortened andthe fabrication cost can be reduced for a TFT array substrate includedin an MVA liquid crystal display.

Embodiment 2

A TFT array substrate 30 b according to Embodiment 2 of the inventionwill now be described with reference to FIGS. 19 through 29. In thisembodiment, like reference numerals are used to refer to like elementsshown in FIGS. 1 through 18 so as to omit the detailed description.

The TFT array substrate 30 b is included in a liquid crystal displaytogether with an opposing counter substrate and a liquid crystal layersandwiched between these substrates in the same manner as the TFT arraysubstrate 30 a of Embodiment 1.

In this TFT array substrate 30 b, a gate line, a gate electrode 4 a anda gate line external leading electrode 4 b are formed in a three-layeredstructure of a gate first metal layer 21 a, a gate second metal layer 22a and a gate third metal layer 23 a; a semiconductor layer 24 a, asource electrode 25 b and a drain electrode 25 c are formed in aone-layered structure; and a pixel electrode 25 d is formed in atwo-layered structure of the semiconductor layer 24 a and the drainelectrode 25 c. The rest of the structure is the same as that of the TFTarray substrate 30 a of Embodiment 1 and hence the description isomitted.

Next, a method for fabricating the TFT array substrate 30 b ofEmbodiment 2 will be described. This TFT array substrate 30 b isfabricated through a first step of a gate electrode forming procedure; asecond step including a laminated body forming procedure, a first resistpattern forming procedure, a first etching procedure, a second resistpattern forming procedure and a second etching procedure; and a thirdstep of a pixel electrode forming procedure.

First, in the gate electrode forming procedure, a gate first metal film21 (with a thickness of approximately 500 Å) of a titanium film, a gatesecond metal film 22 (with a thickness of approximately 3000 Å) of analuminum film and a gate third metal film 23 (with a thickness ofapproximately 1000 Å) of a titanium nitride film are successively formedon an insulating substrate 1 of, for example, a glass substrate by thesputtering, so as to form a first metal laminated film 19 a as shown inFIG. 19. Thereafter, the first metal laminated film 19 a is patterned bythe photolithography, so as to form a gate electrode 4 a, a gate lineand a gate line external leading electrode 4 b all composed of a gatefirst metal layer 21 a, a gate second metal layer 22 a and a gate thirdmetal layer 23 a.

At this point, the metal film used as the gate first metal layer 21 a isnot particularly specified and is, for example, a titanium film, achromium film, a molybdenum film or the like. Also, the metal film usedas the gate second metal layer 22 a is not particularly specified andis, for example, an aluminum film, a tantalum film, a titanium film orthe like. Among these exemplified metal films, an aluminum film ispreferably used. Furthermore, the metal film used as the gate thirdmetal layer 23 a is not particularly specified and is, for example, atitanium film, a titanium nitride film or the like. The reason why thesemetal films are selected will be described later.

In the multilayered body forming procedure subsequently performed, agate insulating film 5 (with a thickness of approximately 4000 Å) of asilicon nitride film is first deposited by the plasma CVD over thesubstrate on which the gate electrode 4 a, the gate line and the gateline external leading electrode 4 b have been formed as shown in FIG.21. Then, a semiconductor film 24 (with a thickness of approximately1500 Å) of a zinc oxide film is deposited by pulse laser CVD over thesubstrate on which the gate insulating film 5 has been formed.Furthermore, a transparent conducting film 25 (with a thickness ofapproximately 1000 Å) of an ITO film is deposited by the sputtering overthe substrate on which the semiconductor film 24 has been formed.

Thus, a multilayered body 18 including the gate insulating film 5, thesemiconductor film 24 and the transparent conducting film 25 stacked inthis order in the upward direction is formed. At this point, aconducting film 12 is composed of merely the ITO film used as thetransparent conducting film 25.

The semiconductor film 24 may be made of, apart from the exemplifiedzinc oxide film, a material having higher transmissivity than amorphoussilicon with the same thickness, such as a zinc magnesium oxide film, azinc cadmium oxide film or a cadmium oxide film.

Furthermore, the semiconductor film 24 may be doped with an impuritysuch as phosphorus to the extent that its transparency is not spoiled inorder to attain desired mobility and a desired on/off ratio (that is, aratio between a current passing in an on state and a leakage currentcaused in an off state in switching a drain current with a gatevoltage).

The material for the transparent conducting film 25 is not particularlylimited to the ITO film but may be any film with a desired resistancevalue such as an IZO (indium zinc oxide) film, a zinc oxide film, a tinoxide film or the like.

Owing to this structure, since a lower layer of the transparentconducting film 25 included in a pixel electrode 25 d is made of thezinc oxide film 24 with a transparent property, the transmissivity in aregion corresponding to the pixel electrode 25 d can be improved, so asto improve the contrast and the brightness of the liquid crystaldisplay.

Also, since the conducting film is composed of merely the transparentconducting film 25, there is no need to expose the transparentconducting film by etching a metal film as in Embodiment 1 in the thirdstep described below. Therefore, a pixel electrode 25 e can be formed bymerely forming a protection masking layer 17 a and a projection 17 b inthe third step. Thus, the fabrication process of the TFT array substratecan be shortened and the fabrication cost thereof can be reduced.

In the first resist pattern forming procedure subsequently performed, aresist film is first formed by applying a resist of a photosensitiveresin over the substrate. Then, the resist film formed over thesubstrate is made into a first resist pattern 13 a having a plurality ofthicknesses as shown in FIG. 22 with exposure adjusted by using a slitmask or the like.

At this point, the first resist pattern 13 a includes a first opening 14a exposing the conducting film (the ITO film 25) and disposed above aportion other than a region where a channel portion C, a source line, asource electrode 25 c and a drain electrode 25 d are formed; and asecond opening 14 b having a bottom portion with a given thickness anddisposed above the gate electrode 4 a, and more specifically above aportion corresponding to the channel portion C. An appropriate ratio inthe thickness between the resist film in the second opening 14 b and theresist film in another portion is varied in accordance with theconditions for etching subsequently performed, and the resist film has athickness of, for example, approximately 15000 through 20000 Å in thesecond opening 14 b and approximately 40000 Å in another portion.

In the first etching procedure subsequently performed, the semiconductorfilm 24 and the transparent conducting film 25 are etched by using thefirst resist pattern 13 a as a mask, so as to form a source/drainforming portion 12 a composed of a semiconductor layer 24 a and atransparent conducting layer 25 a as shown in FIG. 23.

In the second resist pattern forming procedure subsequently performed,the first resist pattern 13 a is wholly ashed as shown in FIG. 24. Thus,the thickness of the first resist pattern 13 a is reduced as a whole andthe bottom portion of the second opening 14 b is removed, so as to forma second resist pattern 13 b in which the ITO layer 25 a is exposed.

In the second etching procedure subsequently performed, the transparentconducting layer 25 a is first etched by using the second resist pattern13 b as a mask, so as to form a source electrode 25 b, a drain electrode25 c, a source line and a source line external leading electrode.Thereafter, the second resist pattern 13 b is removed from thesubstrate. Thus, a TFT 20 is formed.

In the pixel electrode forming procedure subsequently performed, asilicon nitride film (with a thickness of approximately 2000 Å) is firstdeposited over the substrate by the plasma CVD, so as to form aprotection film 15.

Thereafter, in the same manner as in Embodiment 1, an orientationcontrolling film 16 (with a thickness of approximately 1.0 μm through3.0 μm) is formed on the protection film 15 by the spin coating or thelike as shown in FIG. 26.

Furthermore, the orientation controlling film 16 formed over thesubstrate is subjected to exposure with a photomask used, developmentand post-bake, so as to form a masking layer 16 a and a projection upperportion 16 b.

Then, the protection film 15 is etched by using the masking layer 16 aand the projection upper portion 16 b as a mask, so as to form aprotection masking layer 17 a composed of the masking layer 16 a and aprotection layer 15 a for covering the TFT 20; a projection 17 bcomposed of the projection upper portion 16 b and a projection lowerportion 15 b; and a pixel electrode 25 d. Thus, the TFT array substrate30 b as shown in FIG. 27 is fabricated. Also, the protection maskinglayer 17 a is formed so as to cover not only the TFT 20 but also gatelines 2 and source lines 6 for functioning as a black matrix.

At this point, the gate line external leading electrode 4 b and thesource line external leading electrode will be described in more detail.

FIG. 28 is a schematic plan view of an end portion of the TFT arraysubstrate 30 b in which a plurality of gate line external leadingelectrodes 4 b are formed, and FIG. 29 is a schematic cross-sectionalview thereof taken on line XXIX-XXIX of FIG. 28.

Each gate line external leading electrode 4 b is exposed, simultaneouslywith the formation of the pixel electrode 25 d and the like, by forminga contact hole 17 e in a portion of the multilayered film of the gateinsulating film 5, the protection film 15 and the orientationcontrolling film 16 stacked on the gate line external leading electrode4 b and disposed inside the periphery of the gate line external leadingelectrode 4 b. Therefore, the aluminum film included in the gate secondmetal layer 22 a of the first metal laminated film 19 a, which can beeasily oxidized, is not exposed. Also, the gate third metal layer 23 a,namely, the uppermost layer of the first metal laminated film 19 aexposed by the etching, is a titanium nitride film minimally oxidized.Owing to this structure, the gate line external leading electrode 4 bhas a structure minimally oxidized. Accordingly, the gate line externalleading electrode 4 b and an external driver circuit can be definitelyelectrically connected to each other, so as to improve the reliability.Moreover, there is no need to form the gate line external leadingterminal 4 c by etching the gate second metal layer 3 a (of the aluminumfilm) easily oxidized as in Embodiment 1, and hence, the fabricationprocess can be shortened and the fabrication cost can be reduced.

Furthermore, since a titanium nitride film or a titanium film has ahigher adhesion property to the silicon nitride film used as the gateinsulating film 5 than an aluminum film, the film is minimally peeledoff and stable fabrication yield can be attained.

The source line external leading electrode is exposed, simultaneouslywith the formation of the pixel electrode 25 d and the like, withoutetching the second metal laminated film 19 b as in Embodiment 1 butmerely by etching the protection film 15 and the orientation controllingfilm 16 formed thereon.

Since the gate second metal layer 22 a is an aluminum film in thisembodiment, an effect to lower the wiring resistance of the gate linecan be attained. Moreover, since the gate third metal layer 23 a formedthereon is a titanium nitride film, the formation of a hillock on thealuminum film can be suppressed, so as to reduce interlayer leakagebetween a gate line and a source line otherwise caused by a hillock.

In this manner, in the fabrication method of this embodiment, the TFTarray substrate 30 b is fabricated through the three photolithographyprocesses of the first, second and third steps including the formationof the protection masking layer 17 a covering the TFT 20 and working asa black matrix between pixels, the formation of the projection 17 b usedfor realizing the MVA and the formation of the gate line externalleading electrode 4 b and the source line external leading electrode.Therefore, the fabrication process can be shortened and the fabricationcost can be reduced for a TFT array substrate included in an MVA liquidcrystal display.

INDUSTRIAL APPLICABILITY

As described above, the present invention is useful for an MVA liquidcrystal display because the fabrication process can be shortened and thefabrication cost can be reduced for a TFT array substrate included inthe MVA liquid crystal display.

1. A method for fabricating a thin film transistor array substrateincluding a plurality of pixels provided on a substrate; a plurality ofthin film transistors each of which is disposed correspondingly to eachof the plurality of pixels and includes a gate electrode, a sourceelectrode, a drain electrode and a semiconductor layer having a channelportion formed correspondingly to the gate electrode; a source lineconnected to the source electrode; a pixel electrode connected to thedrain electrode for applying a voltage through a liquid crystal layerincluding liquid crystal molecules; and a projection provided in thepixel electrode for controlling orientation of the liquid crystalmolecules, comprising: a first step of forming a pattern of the gateelectrode on the substrate by photolithography; a second step of forminga pattern of the thin film transistors by forming a multilayered body bystacking, on the substrate where the gate electrode has been formed, agate insulating film, a semiconductor film to be made into thesemiconductor layer and a conducting film including a transparentconducting film and covering the semiconductor film, and by patterningthe multilayered body by photolithography; and a third step of forming aprotection layer covering the thin film transistors and the projectionand of forming the pixel electrode by exposing a part of the transparentconducting film by photolithography, the second step including a resistpattern forming procedure for forming a resist film covering themultilayered body, and forming, in the resist film, a first openingexposing the conducting film therein and disposed above a portion otherthan a region where the channel portion, the source line, the sourceelectrode and the drain electrode are formed, and a second openinghaving a bottom portion with a given thickness and disposed above aportion of the multilayered body corresponding to the channel portion; afirst etching procedure for etching the conducting film exposed in thefirst opening and the semiconductor film disposed beneath the conductingfilm; and a second etching procedure for removing the bottom portion ofthe second opening for etching the conducting film exposed therein. 2.The method of fabricating a thin film transistor array substrate ofclaim 1, wherein the conducting film has a masking property, and aportion of the conducting film disposed inside the periphery of thedrain electrode is etched in the third step.
 3. The method offabricating a thin film transistor array substrate of claim 1, whereinthe semiconductor film includes an upper first semiconductor film and alower second semiconductor film, and the exposed conducting film and thefirst semiconductor film are etched in the second etching procedure. 4.The method of fabricating a thin film transistor array substrate ofclaim 1, wherein a masking layer is formed as an upper layer or a lowerlayer of the protection layer, and the masking layer is formedsimultaneously with the protection layer in the third step.
 5. Themethod of fabricating a thin film transistor array substrate of claim 1,wherein the protection layer is made of a material with a maskingproperty.
 6. The method of fabricating a thin film transistor arraysubstrate of claim 1, wherein the gate electrode is made of a firstmetal laminated film including a plurality of metal films stacked on oneanother, and the first metal laminated film includes a metal film madeof an aluminum film or an aluminum alloy film.
 7. The method offabricating a thin film transistor array substrate of claim 1, whereinthe conducting film includes a single layer of the transparentconducting film.
 8. The method of fabricating a thin film transistorarray substrate of claim 1, wherein the conducting film includes thetransparent conducting film made of a compound of indium oxide and tinoxide, and a second metal laminated film covering the transparentconducting film and including a plurality of metal films stacked on oneanother, and the second metal laminated film includes a lower layer of amolybdenum film or a molybdenum alloy film and an upper layer of analuminum film or an aluminum alloy film.
 9. The method of fabricating athin film transistor array substrate of claim 1, wherein thesemiconductor film is made of a material with higher transmissivity thanamorphous silicon with the same thickness.
 10. The method of fabricatinga thin film transistor array substrate of claim 1, wherein a pluralityof gate lines each connected to the gate electrode and a gate lineexternal leading electrode corresponding to an extended portion of eachgate line are formed simultaneously with the gate electrode in the firststep.
 11. The method of fabricating a thin film transistor arraysubstrate of claim 10, wherein the gate electrode, the gate line and thegate line external leading electrode are made of a first metal laminatedfilm including a plurality of metal films stacked on one another, thefirst metal laminated film includes a titanium film or a titanium alloyfilm as a lowermost layer, and a portion of the titanium film or thetitanium alloy film corresponding to the gate line external leadingelectrode is exposed by etching in the third step.
 12. The method offabricating a thin film transistor array substrate of claim 11, whereinthe first metal laminated film includes the titanium film or thetitanium alloy film as the lowermost layer, a metal film made of analuminum film or an aluminum alloy film, and a molybdenum film or amolybdenum alloy film covering the metal film.
 13. The method offabricating a thin film transistor array substrate of claim 10, whereinthe gate electrode, the gate line and the gate line external leadingelectrode are made of a first metal laminated film including a pluralityof metal films stacked on one another, and the first metal laminatedfilm includes a titanium film or a titanium alloy film as an uppermostlayer.
 14. The method of fabricating a thin film transistor arraysubstrate of claim 13, wherein the first metal laminated film includesan aluminum film or an aluminum alloy film, and portions of theprotection layer and the gate insulating film disposed inside theperiphery of the gate line external leading electrode are etched in thethird step.
 15. The method of fabricating a thin film transistor arraysubstrate of claim 10, wherein the source line and a source lineexternal leading electrode corresponding to an extended portion of thesource line are formed along a direction crossing the plurality of gatelines simultaneously with the source electrode in the second step. 16.The method of fabricating a thin film transistor array substrate ofclaim 15, wherein the gate electrode, the gate line and the gate lineexternal leading electrode are made of a first metal laminated filmincluding a plurality of metal films stacked on one another, the sourceelectrode, the source line and the source line external leadingelectrode are made of a second metal laminated film including aplurality of metal films stacked on one another, and at least uppermostlayers of the first metal laminated film and the second metal laminatedfilm are removed by etching in portions corresponding to the gate lineexternal leading electrode and the source line external leadingelectrode in the third step.
 17. The method of fabricating a thin filmtransistor array substrate of claim 16, wherein the uppermost layer ofeach of the first metal laminated film and the second metal laminatedfilm is made of an aluminum film or an aluminum alloy film, or amultilayered film of a molybdenum film or a molybdenum alloy filmstacked on an aluminum film or an aluminum alloy film.
 18. The method offabricating a thin film transistor array substrate of claim 15, whereinthe protection layer has a masking property and covers the thin filmtransistors, the gate line and the source line.
 19. The method offabricating a thin film transistor array substrate of claim 15, whereinthe gate line external leading electrode and the source line externalleading electrode are exposed by forming one opening correspondingly toat least one of the gate line external leading electrode and the sourceline external leading electrode by etching.
 20. The method offabricating a thin film transistor array substrate of claim 1, wherein aprotection film included in the protection layer and the gate insulatingfilm are etched in portions outside the periphery of the drain electrodein the third step.
 21. A thin film transistor array substratecomprising: a plurality of pixels provided on a substrate; a pluralityof thin film transistors each of which is disposed correspondingly toeach of the plurality of pixels and includes a gate electrode, a sourceelectrode, a drain electrode and a semiconductor layer having a channelportion formed correspondingly to the gate electrode; a source lineconnected to the source electrode; a pixel electrode connected to thedrain electrode for applying a voltage through a liquid crystal layerincluding liquid crystal molecules; and a projection provided in thepixel electrode for controlling orientation of the liquid crystalmolecules, the thin film transistor array substrate being fabricatedthrough: a first step of forming a pattern of the gate electrode on thesubstrate by photolithography; a second step of forming a pattern of thethin film transistors by forming a multilayered body by stacking, on thesubstrate where the gate electrode has been formed, a gate insulatingfilm, a semiconductor film to be made into the semiconductor layer and aconducting film including a transparent conducting film and covering thesemiconductor film, and patterning the multilayered body byphotolithography; and a third step of forming a protection layercovering the thin film transistors and the projection and of forming thepixel electrode by exposing a part of the transparent conducting film byphotolithography, the second step including a resist pattern formingprocedure for forming a resist film covering the multilayered body, andforming, in the resist film, a first opening exposing the conductingfilm therein and disposed above a portion other than a region where thechannel portion, the source line, the source electrode and the drainelectrode are formed, and a second opening having a bottom portion witha given thickness and disposed above a portion of the multilayered bodycorresponding to the channel portion; a first etching procedure foretching the conducting film exposed in the first opening and thesemiconductor film disposed beneath the conducting film; and a secondetching procedure for removing the bottom portion of the second openingfor etching the conducting film exposed therein, the semiconductor filmand the conducting film covering the semiconductor film being providedbeneath the projection.